Portrait of Zixuan Wang
Zixuan Wang

Summary

I am Zixuan Wang (王子轩), a software engineer at Apple working on CloudOS. I received my PhD from the University of California San Diego, where I worked with Prof. Jishen Zhao on architecture and systems research. I also worked with Prof. Steven Swanson at NVSL Lab, UCSD.

My research focuses on building scalable and secure systems with emerging architecture, systems, and programming technologies. At each level, I conduct systematic analysis, from characterizing performance to attacking and securing the system to developing programming support.

My industrial work across multiple companies has focused on deploying emerging technologies in real-world systems, especially trusted execution using confidential virtual machines. At Google in 2021, I worked on modernizing the Linux KVM testing framework with UEFI and AMD SEV/SEV-ES support, which became the first such contribution merged into the Linux KVM community. At Meta in 2022, I worked on the initial confidential virtual machine platform by initiating and developing the system and software support, and the work was highlighted at Meta's Annual Security Summit. At Google in 2023, I enhanced guest confidential computing with measurable hypervisor service code by leveraging AMD SEV-SNP SVSM. Previously at SK hynix in 2019, I worked on early evaluation of CXL prototypes, which led to one of the first publications on CXL systems.

Work Experience

Senior Software Engineer

  • Apple
  • 2025 Apr - Present

I am working on private cloud computing and CloudOS at Apple.

Software Engineer

  • Apple
  • 2024 Sept - 2025 Apr

I worked on private cloud computing and CloudOS at Apple.

Graduate Research Assistant

  • University of California, San Diego
  • 2018 Sept - 2024 Aug

I worked in STABLE Lab and NVSL Lab on architecture and systems design for memory and secure systems.

  • Hiemdall: a heterogeneous system benchmarking framework demonstrated on multiple CXL-based systems.
  • NVLeak: an off-chip memory architecture reverse engineering and covert/side-channel attack framework.
  • COARSE: a disaggregated memory system for distributed deep learning training.
  • Ayudante: a learning-based persistent memory automatic programming framework.
  • LENS: a profiler that discovers NVRAM DIMM microarchitecture design.
  • VANS: a cycle-level NVRAM simulator validated against real products.

Software Engineering Intern

  • Google
  • 2023 June - 2023 Sept

Built AMD SEV-SNP SVSM support in Google Cloud to enhance confidential computing. I received a peer bonus for this work.

Student Researcher

  • Meta
  • 2022 Sept - 2023 Jan

Deployed the first confidential virtual machine platform at Meta.

Software Engineering Intern

  • Meta
  • 2022 June - 2022 Sept

Initiated and developed confidential virtual machine platform support at Meta.

Software Engineering Intern

  • Google
  • 2021 June - 2021 Sept

Developed UEFI and AMD SEV/SEV-ES support for KVM-unit-tests. The code was merged by the Linux KVM community, and I received two peer bonuses during this internship.

Research Intern

  • SOLAB, SK hynix America
  • 2019 June - 2019 Sept

Evaluated the performance of CXL memory prototypes and enabled GPU direct access to coherent off-chip memory.

Undergraduate Research Assistant

  • Zhejiang University
  • 2015 - 2018

I worked in the Computer Architecture Lab on operating systems and computer architecture.

  • Developed the ZJUNIX operating system from scratch and ran it on a self-designed MIPS SoC on FPGA.
  • Built an FPGA accelerator for high-frequency trading.
  • Worked on the portable modular 3D bioprinter project, which earned the Outstanding Prize in Challenge Cup.

Publications

HybridTier: an Adaptive and Lightweight CXL-Memory Tiering System

  • ASPLOS'26

Kevin Song, Jiacheng Yang, Zixuan Wang, Jishen Zhao, Sihang Liu, Gennady Pekhimenko

COLA: Characterizing and Optimizing the Tail Latency for Safe Level-4 Autonomous Vehicle Systems

  • ICRA'25

Haolan Liu, Zixuan Wang, Jishen Zhao

The Hitchhiker's Guide to Programming and Optimizing CXL-Based Heterogeneous Systems

  • ArXiv'24

Zixuan Wang, Suyash Mahar, Luyi Li, Jangseon Park, Jinpyo Kim, Theodore Michailidis, Yue Pan, Tajana Rosing, Dean Tullsen, Steven Swanson, Kyung Chang Ryoo, Sungjoo Park, Jishen Zhao

Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction

  • ArXiv'24

Hanxian Huang, Zhenghan Lin, Zixuan Wang, Xin Chen, Ke Ding, Jishen Zhao

Fork is All You Need in Heterogeneous Systems

  • ASPLOS HCDS Workshop'24

Zixuan Wang, Jishen Zhao

CXLeak: Architectural Attacks via Practical CXL Systems

  • Work in Progress

Zixuan Wang, et al.

NVLeak: Off-Chip Side-Channel Attacks via Non-Volatile Memory Systems

  • USENIX Security'23

Zixuan Wang, Mohammadkazem Taram, Daniel Moghimi, Steven Swanson, Dean Tullsen, Jishen Zhao

Characterizing WebAssembly Performance in the Era of Serverless Computing

  • ISSTA'23 SRC

Jamshed Ashurov, Zixuan Wang, Jishen Zhao

Enabling Efficient Large-Scale Deep Learning Training with Cache Coherent Disaggregated Memory Systems

  • HPCA'22

Zixuan Wang, Joonseop Sim, Euicheol Lim, Jishen Zhao

Enabling Fast Recovery for Autonomous Vehicle Systems with Linux Container Checkpointing

  • SOSP'21 SRC

Maximilian Apodaca, Shengye Wang, Zixuan Wang, Jishen Zhao

Ayudante: A Deep Reinforcement Learning Approach to Assist Persistent Memory Programming

  • ATC'21

Hanxian Huang, Zixuan Wang, Juno Kim, Steven Swanson, Jishen Zhao

Characterizing and Modeling Non-Volatile Memory Systems

  • IEEE Micro TopPicks'21

Zixuan Wang, Xiao Liu, Jian Yang, Theodore Michailidis, Steven Swanson, Jishen Zhao

Basic Performance Measurements of the Intel Optane DC Persistent Memory Module

  • ArXiv'19

Joseph Izraelevitz, Jian Yang, Lu Zhang, Juno Kim, Xiao Liu, Amirsaman Memaripour, Yun Joon Soh, Zixuan Wang, Yi Xu, Subramanya R Dulloor, Jishen Zhao, Steven Swanson

Reliable and Flexible Large Scale Memory Network

  • NVMW'19

Zixuan Wang, Xiao Liu, Jongryool Kim, Hokyoon Lee, Jishen Zhao

A Modulized Portable 3D Bioprinter

  • China Patent

Zixuan Wang, Bin Zhang, Wenzheng Kuang, Huayong Yang

Projects

Architectural Security Attacks in Main Memory Systems

  • June 2023

Side-channel attacks in non-volatile main memory systems.

  • Software-based reverse engineering of the microarchitecture of non-volatile main memory.
  • Side-channel attacks that leak sensitive data such as database tables and private encryption keys.

Technologies: C, x86 Assembly, Linux Kernel, Reverse Engineering, Side-Channel Attacks.

Trusted Execution of Hypervisor Code within Guest Virtual Machine

  • June 2023

Initiated AMD SEV-SNP SVSM support to enhance Google Cloud confidential virtual machines.

Built the initial SVSM support in Google Cloud's Linux kernel, hypervisor, guest firmware, and guest kernel.

Technologies: C, x86 Assembly, KVM, UEFI, AMD SEV-SNP, AMD SVSM, Rust.

Confidential Virtual Machine Platform

  • June 2022

Initiated and developed the first confidential VM platform at Meta, later highlighted at Meta's Annual Security Summit.

Built the initial software and operating system support for the first confidential virtual machine platform at Meta.

Technologies: QEMU, C++, x86 Assembly, KVM, UEFI, AMD SEV, Rust.

KVM-unit-tests under UEFI and AMD SEV/SEV-ES

  • Sep. 2021

Started as my 2021 Google internship project and later continued in spare time.

  • Implemented UEFI support as an alternative to the existing SeaBIOS plus Multiboot flow.
  • Implemented AMD SEV and SEV-ES support for a widely adopted KVM testing framework.

Technologies: C, x86 Assembly, KVM, SeaBIOS, UEFI, AMD SEV, AMD SEV-ES, GNU Toolchain, Linker Script.

Accelerating Distributed Training of LLM

  • Oct. 2021

Built a CXL-based disaggregated memory system for large-model training infrastructure. Accepted by HPCA 2022.

  • Built a disaggregated memory prototype in FPGA.
  • Enabled multi-GPU training with effectively expanded memory using CXL-based off-chip memory.

Technologies: CXL, FPGA, TensorFlow, CUDA, Verilog.

LENS: A Low-Level NVRAM Profiler

  • Sep. 2020

MICRO 2020 paper: Characterizing and Modeling Non-Volatile Memory Systems.

  • Built the first profiler that can discover non-volatile memory on-DIMM microarchitecture.
  • Runs in Linux kernel space with microbenchmarks written in x86 assembly.
  • Source code

Technologies: C, Linux Kernel, x86 Assembly.

VANS: A Validated NVRAM Simulator

  • Sep. 2020

MICRO 2020 paper: Characterizing and Modeling Non-Volatile Memory Systems.

  • Built a cycle-level NVRAM simulator validated against Intel Optane persistent memory.
  • Used modern C++ to simplify the implementation and improve simulator throughput.
  • Source code

Technologies: C++17, Python, R, Cycle-Accurate Simulation.

GPU Direct Access to Cache-Coherent Off-Chip Memory

  • Sep. 2019

Work completed during my SK hynix internship.

  • Evaluated the GEN-Z memory prototype and developed a framework for GPU direct access through PCIe.
  • Showed up to 16x faster cuDF performance compared with indirect CPU-mediated access.

Technologies: FPGA, GPU, Linux, GEN-Z, CXL.

FPGA Accelerated High-Frequency Trading

  • Sep. 2018

Deployed in a production environment.

  • Offloaded decision procedures to FPGA and forwarded network data directly to the accelerator.
  • Used 10 Gigabit Ethernet for communication between FPGA and host PC.

Technologies: FPGA, Linux, Userspace IO, MIPS Assembly.

QEMU micro:bit Emulator

  • May. 2018

A micro:bit emulator based on QEMU.

  • Implemented Cortex-M0 features on top of QEMU's Cortex-M3 emulator.
  • Added peripheral emulators including LED matrix, timer, clock generator, and random number generator.
  • Reverse engineered the micro:bit bootloader and validated the hardware emulation with Mbed OS.
  • Source code

Technologies: C, ARM Assembly, ARM Mbed OS, Bootloader, QEMU.

ZJUNIX Operating System

  • Apr. 2017

An operating system built from scratch and running on a self-designed SoC.

  • Implemented bootloader, interrupts and exceptions, and kernel memory management.
  • Built process scheduling, shell and core userland utilities, FAT and ext2 filesystem support.

Technologies: Open Source, OS Design, Bootloader, C, MIPS Assembly, Linker Script.

ZJU-SoC

  • Dec. 2016

An SoC built from scratch using FPGA.

  • Implemented a 5-stage pipeline MIPS32 CPU with 93 instructions and two levels of cache.
  • Integrated DDR3, VGA, PS/2, and SD controller peripherals.
  • Capable of running both ZJUNIX and Arduino programs.

Technologies: Open Source, FPGA, Verilog, CPU Design, Peripheral Design.

Portable 3D Bioprinter

  • Dec. 2016

A portable modular 3D bioprinter that prints tissue directly on wounds.

  • Demo video
  • Used FPGA-accelerated edge detection to meet real-time requirements.
  • Resulted in utility model patent 201720246090.1 and multiple awards.

Technologies: Image Processing, Mechanical Design, Real-Time Systems.

FPGA Accelerated Fluid Simulation

  • Aug. 2016

An FPGA acceleration of PCISPH fluid simulation.

  • Used FPGA for simulation and PC for rendering.
  • FPGA communicated with PC through Ethernet.
  • Won second prize in Digilent Design Contest China 2017.

Technologies: Graphics Engine, FPGA.

Projects for Fun

VS Code LinkerScript

  • Aug. 2018

The first GNU linker script highlighting extension for VS Code, based on TextMate grammars.

Technologies: VS Code Extension, YAML, Linker Script.

ZJU Thesis

  • May. 2018

LaTeX template for Zhejiang University graduate design and thesis.

  • Recommended by the School of Undergraduates.

Technologies: LaTeX.

Makefile Templates

  • July 2017

Makefile templates for C and C++ projects.

Technologies: Makefile.

Chinese Input Method in MIPS

  • July 2016

A Chinese input method written in pure MIPS assembly.

  • Implemented pinyin input and GB2312 lookup in roughly 2,000 lines of MIPS assembly.
  • Demo picture

Technologies: MIPS Assembly, Keyboard Interrupt, VGA Display.

Tiger Language Compiler

  • May 2017

A simple compiler for the Tiger programming language.

  • Implemented lexical analysis, parsing, abstract syntax tree generation, and intermediate code generation.

Technologies: Bison, Flex, C++11/14.